Information

UARTx_C5 field descriptions (continued)
Field Description
NOTE: If C2[RIE] is cleared, the RDRF DMA and RDFR interrupt request signals are not asserted when
the S1[RDRF] flag is set, regardless of the state of RDMAS.
0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to
request interrupt service.
1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a
DMA transfer.
4–0
Reserved
This read-only field is reserved and always has the value zero.
45.3.13 UART Extended Data Register (UARTx_ED)
This register contains additional information flags that are stored with a received
dataword. This register may be read at any time but only contains valid data if there is a
dataword in the receive FIFO.
NOTE
The data contained in this register represents additional
information regarding the conditions on which a dataword was
received. The importance of this data varies with application,
and in some cases maybe completely optional. These fields
automatically update to reflect the conditions of the next
dataword whenever D is read.
NOTE
If the S1[NF] and S1[PF] flags have not been set since the last
time the receive buffer was empty, the NOISY and PARITYE
bits will be zero.
Addresses: UART0_ED is 4006_A000h base + Ch offset = 4006_A00Ch
UART1_ED is 4006_B000h base + Ch offset = 4006_B00Ch
UART2_ED is 4006_C000h base + Ch offset = 4006_C00Ch
UART3_ED is 4006_D000h base + Ch offset = 4006_D00Ch
UART4_ED is 400E_A000h base + Ch offset = 400E_A00Ch
UART5_ED is 400E_B000h base + Ch offset = 400E_B00Ch
Bit 7 6 5 4 3 2 1 0
Read NOISY PARITYE 0
Write
Reset
0 0 0 0 0 0 0 0
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1278 Freescale Semiconductor, Inc.