Information

UARTx_IR field descriptions
Field Description
7–3
Reserved
This read-only field is reserved and always has the value zero.
2
IREN
Infrared enable
This bit enables/disables the infrared modulation/demodulation.
0 IR disabled.
1 IR enabled.
1–0
TNP
Transmitter narrow pulse
These bits enable whether the UART transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse.
00 3/16.
01 1/16.
10 1/32.
11 1/4.
45.3.16 UART FIFO Parameters (UARTx_PFIFO)
This register provides the ability for the programmer to turn on and off FIFO
functionality. It also provides the size of the FIFO that has been implemented. This
register may be read at any time. This register should only be written when the C2[RE]
and C2[TE] bits are cleared / not set and when the data buffer/FIFO is empty.
Addresses: UART0_PFIFO is 4006_A000h base + 10h offset = 4006_A010h
UART1_PFIFO is 4006_B000h base + 10h offset = 4006_B010h
UART2_PFIFO is 4006_C000h base + 10h offset = 4006_C010h
UART3_PFIFO is 4006_D000h base + 10h offset = 4006_D010h
UART4_PFIFO is 400E_A000h base + 10h offset = 400E_A010h
UART5_PFIFO is 400E_B000h base + 10h offset = 400E_B010h
Bit 7 6 5 4 3 2 1 0
Read
TXFE
TXFIFOSIZE
RXFE
RXFIFOSIZE
Write
Reset
0 * * * 0 * * *
* Notes:
TXFIFOSIZE bitfield: The reset value depends on whether the specific UART instance supports the FIFO and on the size of
that FIFO. See the Chip Configuration details for more information on the FIFO size supported for
each UART instance.
•
RXFIFOSIZE bitfield: The reset value depends on whether the specific UART instance supports the FIFO and on the size of
that FIFO. See the Chip Configuration details for more information on the FIFO size supported for
each UART instance.
•
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1281