Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 144 (13x13) 32-Bit 100 MHz I/O number 104

1281

UARTx_PFIFO field descriptions

Field Description

TXFE

Transmit FIFO Enable

When this bit is set the built in FIFO structure for the transmit buffer is enabled. The size of the FIFO

structure is indicated by the TXFIFOSIZE field. If this bit is not set then the transmit buffer operates as a

FIFO of depth one dataword regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be

cleared prior to changing this bit. Additionally TXFLUSH and RXFLUSH commands should be issued

immediately after changing this bit.

0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).

1 Transmit FIFO is enabled. Buffer is depth indicted by TXFIFOSIZE.

6–4

TXFIFOSIZE

Transmit FIFO. Buffer Depth

The maximum number of transmit datawords that can be stored in the transmit buffer. This field is read

only.

000 Transmit FIFO/Buffer Depth = 1 Dataword.

001 Transmit FIFO/Buffer Depth = 4 Datawords.

010 Transmit FIFO/Buffer Depth = 8 Datawords.

011 Transmit FIFO/Buffer Depth = 16 Datawords.

100 Transmit FIFO/Buffer Depth = 32 Datawords.

101 Transmit FIFO/Buffer Depth = 64 Datawords.

110 Transmit FIFO/Buffer Depth = 128 Datawords.

111 Reserved.

RXFE

Receive FIFO Enable

When this bit is set the built in FIFO structure for the receive buffer is enabled. The size of the FIFO

structure is indicated by the RXFIFOSIZE field. If this bit is not set then the receive buffer operates as a

FIFO of depth one dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be

cleared prior to changing this bit. Additionally TXFLUSH and RXFLUSH commands should be issued

immediately after changing this bit.

0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)

1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.

2–0

RXFIFOSIZE

Receive FIFO. Buffer Depth

The maximum number of receive datawords that can be stored in the receive buffer before an overrun

occurs. This field is read only.

000 Receive FIFO/Buffer Depth = 1 Dataword.

001 Receive FIFO/Buffer Depth = 4 Datawords.

010 Receive FIFO/Buffer Depth = 8 Datawords.

011 Receive FIFO/Buffer Depth = 16 Datawords.

100 Receive FIFO/Buffer Depth = 32 Datawords.

101 Receive FIFO/Buffer Depth = 64 Datawords.

110 Receive FIFO/Buffer Depth = 128 Datawords.

111 Reserved.

Memory map and registers

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

1282 Freescale Semiconductor, Inc.