Information

UARTx_CFIFO field descriptions (continued)
Field Description
0 RXUF flag does not generate an interrupt to the host.
1 RXUF flag generates an interrupt to the host.
45.3.18 UART FIFO Status Register (UARTx_SFIFO)
This register provides various status information regarding the transmit and receiver
buffers/FIFOs, including interrupt information. This register may be written or read at
anytime.
Addresses: UART0_SFIFO is 4006_A000h base + 12h offset = 4006_A012h
UART1_SFIFO is 4006_B000h base + 12h offset = 4006_B012h
UART2_SFIFO is 4006_C000h base + 12h offset = 4006_C012h
UART3_SFIFO is 4006_D000h base + 12h offset = 4006_D012h
UART4_SFIFO is 400E_A000h base + 12h offset = 400E_A012h
UART5_SFIFO is 400E_B000h base + 12h offset = 400E_B012h
Bit 7 6 5 4 3 2 1 0
Read TXEMPT RXEMPT 0
TXOF RXUF
Write
Reset
1 1 0 0 0 0 0 0
UARTx_SFIFO field descriptions
Field Description
7
TXEMPT
Transmit Buffer/FIFO Empty
This status bit asserts when there is no data in the Transmit FIFO/buffer. This bit does not take into
account data that is in the transmit shift register.
0 Transmit buffer is not empty.
1 Transmit buffer is empty.
6
RXEMPT
Receive Buffer/FIFO Empty
This status bit asserts when there is no data in the receive FIFO/Buffer. This bit does not take into
account data that is in the receive shift register.
0 Receive buffer is not empty.
1 Receive buffer is empty.
5–2
Reserved
This read-only field is reserved and always has the value zero.
1
TXOF
Transmitter Buffer Overflow Flag
This flag indicates that more data has been written to the transmit buffer than it can hold. This bit will
assert regardless of the value of CFIFO[TXOFE]. However, an interrupt will only be issued to the host if
the CFIFO[TXOFE] bit is set. This flag is cleared by writing a "1".
Table continues on the next page...
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1284 Freescale Semiconductor, Inc.