Information

45.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)
This is a read only register that indicates how many datawords are currently in the
transmit buffer/FIFO. It may be read at anytime.
Addresses: UART0_TCFIFO is 4006_A000h base + 14h offset = 4006_A014h
UART1_TCFIFO is 4006_B000h base + 14h offset = 4006_B014h
UART2_TCFIFO is 4006_C000h base + 14h offset = 4006_C014h
UART3_TCFIFO is 4006_D000h base + 14h offset = 4006_D014h
UART4_TCFIFO is 400E_A000h base + 14h offset = 400E_A014h
UART5_TCFIFO is 400E_B000h base + 14h offset = 400E_B014h
Bit 7 6 5 4 3 2 1 0
Read TXCOUNT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_TCFIFO field descriptions
Field Description
7–0
TXCOUNT
Transmit Counter
The value in this register indicates the number of datawords that are in the transmit buffer/FIFO. If a
dataword is in the process of being transmitted (i.e. in the transmit shift register) it is not included in the
count. This value may be used in conjunction with the PFIFO[TXFIFOSIZE] field to calculate how much
room is left in the transmit buffer/FIFO.
45.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)
This register provides the ability to set a programmable threshold for notification of
needing to remove data from the receiver buffer/FIFO. This register may be read at any
time but should only be written when C2[RE] is not asserted. Changing the value in this
register will not clear the S1[RDRF] flag.
Addresses: UART0_RWFIFO is 4006_A000h base + 15h offset = 4006_A015h
UART1_RWFIFO is 4006_B000h base + 15h offset = 4006_B015h
UART2_RWFIFO is 4006_C000h base + 15h offset = 4006_C015h
UART3_RWFIFO is 4006_D000h base + 15h offset = 4006_D015h
UART4_RWFIFO is 400E_A000h base + 15h offset = 400E_A015h
UART5_RWFIFO is 400E_B000h base + 15h offset = 400E_B015h
Bit 7 6 5 4 3 2 1 0
Read
RXWATER
Write
Reset
0 0 0 0 0 0 0 1
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1286 Freescale Semiconductor, Inc.