Information

UARTx_RWFIFO field descriptions
Field Description
7–0
RXWATER
Receive Watermark
When the number of datawords in the Receive FIFO/buffer is equal to or greater than the value in this
register field the event is flagged. An interrupt via S1[RDRF] or a DMA request via C5[RDMAS] will be
generated as determined by C5[RDMAS] and C2[RIE] fields. For proper operation the value in the
RXWATER field must be set to be less than the size of the Receive buffer/FIFO size as indicated by
PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and greater than 0.
45.3.22 UART FIFO Receive Count (UARTx_RCFIFO)
This is a read only register that indicates how many datawords are currently in the receive
buffer/FIFO. It may be read at anytime.
Addresses: UART0_RCFIFO is 4006_A000h base + 16h offset = 4006_A016h
UART1_RCFIFO is 4006_B000h base + 16h offset = 4006_B016h
UART2_RCFIFO is 4006_C000h base + 16h offset = 4006_C016h
UART3_RCFIFO is 4006_D000h base + 16h offset = 4006_D016h
UART4_RCFIFO is 400E_A000h base + 16h offset = 400E_A016h
UART5_RCFIFO is 400E_B000h base + 16h offset = 400E_B016h
Bit 7 6 5 4 3 2 1 0
Read RXCOUNT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_RCFIFO field descriptions
Field Description
7–0
RXCOUNT
Receive Counter
The value in this register indicates the number of datawords that are in the receive buffer/FIFO. If a
dataword is in the process of being received (i.e. in the receive shift register) it is not included in the
count. This value may be used in conjunction with the PFIFO[RXFIFOSIZE] field to calculate how much
room is left in the receive buffer/FIFO.
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1287