Information

45.4.2 Receiver
M
PE
PT
RE
VARIABLE 12-BIT RECEIVE
STOP START
RECEIVE
WAKEUP
DATA BUFFER
INTERNAL BUS
MODULE
SBR12:0
BAUDRATE
CLOCK
RAF
LOGIC
SHIFT DIRECTION
ACTIVE EDGE
DETECT
LBKDE
BRFA4:0
MSBF
GENERATOR
SHIFT REGISTER
M10
RXINV
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
PARITY
LOGIC
CONTROL
RxD
RxD
LOOPS
RSRC
From Transmitter
RECEIVER
SOURCE
CONTROL
7816 LOGIC
To TxD
INFRARED LOGIC
Figure 45-220. UART receiver block diagram
45.4.2.1 Receiver character length
The UART receiver can accommodate 8-, 9-, or 10-bit data characters. The states of the
C1[M] and C1[PE] bits and the C4[M10] bit determine the length of data characters.
When receiving 9 or 10-bit data, bit C3[R8] is the ninth bit (bit 8).
45.4.2.2 Receiver bit ordering
When the S2[MSBF] bit is set, the receiver operates such that the first bit received after
the start bit is the MSB of the data word. Likewise the bit received immediately
preceding the parity bit (or the stop bit if parity is not enabled) is treated as the LSB for
Functional description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1304 Freescale Semiconductor, Inc.