Information

45.4.2.7 Hardware flow control
To support hardware flow control, the receiver can be programmed to automatically
deassert and assert RTS.
• RTS will remain asserted until the transfer is completed, even if the transmitter is
disabled mid way through a data transfer, see Transceiver driver enable using RTS
for more details.
• If the receiver request-to-send functionality is enabled, the receiver automatically
deasserts RTS if the number of characters in the receiver data register is equal to or
greater than receiver data buffer's watermark, RWFIFO[RXWATER].
• The receiver asserts RTS when the number of characters in the receiver data register
is less than the watermark. It is not affected by whether RDRF is asserted.
• Even if RTS is deasserted, the receiver continues to receive characters until the
receiver data buffer is full or is overrun.
• If the receiver request-to-send functionality is disabled, the receiver RTS remains
deasserted.
The following figure shows receiver hardware flow control functional timing. Along with
the actual character itself, RXD shows the start bit. The stop bit also indicated, with a
dashed line if necessary. The watermark is set to 2.
C1
C2
C3
C4
RXD
C3
data
buffer
read
S1[RDRF]
RTS_B
C1 in reception
1
C1
C3
Status
Register 1
read
C1 C2
Figure 45-228. Receiver hardware flow control timing diagram
45.4.2.8 Infrared decoder
The infrared decoder converts the received character from the IrDA format to the NRZ
format used by the receiver. It also has a 16-RT clock counter that filters noise and
indicates when a '1' is being received.
Functional description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1312 Freescale Semiconductor, Inc.