Information

Table 45-238. UART interrupt sources (continued)
Interrupt Source Flag Local enable DMA select
Receiver WT WTWE -
Receiver CWT CWTE -
Receiver BWT BWTE -
Receiver INITD INITDE -
Receiver TXT TXTE -
Receiver RXT RXTE -
Receiver GTV GTVE -
45.6.1 RXEDGIF description
The S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Hence, the
active edge can only be detected when in two wire mode. A RXEDGIF interrupt is only
generated when S2[RXEDGIF] is set. If RXEDGIE is not enabled prior to
S2[RXEDGIF] getting set, an interrupt is not generated until S2[RXEDGIF] bit gets set.
45.6.1.1 RxD edge detect sensitivity
Edge sensitivity can be software programmed to be either falling or rising. The polarity
of the edge sensitivity is selected using the S2[RXINV] bit. To detect falling edge
S2[RXINV] is programmed to zero and to detect rising edge S2[RXINV] is programmed
to one.
Synchronizing logic is used prior to detect edges. Prior to detecting an edge, the receive
data on RxD input must be at the de-asserted logic level. A falling edge is detected when
the RxD input signal is seen as a logic 1 (the deasserted level) during one module clock
cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is
detected when the input is seen as a logic 0 during one module clock cycle and then a
logic 1 during the next cycle.
45.6.1.2 Clearing RXEDGIF interrupt request
Writing a logic 1 to the S2[RXEDGIF] bit immediately clears the RXEDGIF interrupt
request even if the RxD input remains asserted. S2[RXEDGIF] will remain set if another
active edge is detected on RxD while attempting to clear the S2[RXEDGIF] flag by
writing a 1 to it.
System level interrupt sources
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1330 Freescale Semiconductor, Inc.