Information

46.2.2 SDHC block diagram
CMD/
Data
Channel
Tx/Rx
Handler
Data Channel
State Machine
SD Bus
Monitor & Gating
Logic
Control
Logic
Control
CMD Channel
State Machine
CRC
CRCCRC
Advanced DMA
Interface
Register
Bank
R/W
Interrupt
Controller
Status Register
Peripheral bus
Clocks
Interrupt
Internal Dual-Port
128x32-bit Buffer
RAM
Clock Controller and Reset manager
DAT0
SD_CLK
SD_CD#
SD_WP
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
SD_LCTL
SD_VS
Configurable
Buffer
Controller
Crossbar switch
master port
DMA request
Figure 46-2. Enhanced secure digital host controller block diagram
46.2.3 Features
The features of the SDHC module include the following:
• Conforms to the SD Host Controller Standard Specification version 2.0 including test
event register support
• Compatible with the MMC System Specification version 4.2/4.3
• Compatible with the SD Memory Card Specification version 2.0 and supports the
high capacity SD memory card
• Compatible with the SDIO Card Specification version 2.0
• Compatible with the CE-ATA Card Specification version 1.0
Chapter 46 Secured digital host controller (SDHC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1343