Information

Table 46-1. SDHC signal descriptions (continued)
Signal Description I/O
SDHC_D6 DAT6 line in 8-bit mode
Not used in other modes
I/O
SDHC_D7 DAT7 line in 8-bit mode
Not used in other modes
I/O
46.4 Memory map and register definition
This section includes the module memory map and detailed descriptions of all registers.
SDHC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400B_1000 DMA System Address Register (SDHC_DSADDR) 32 R/W 0000_0000h
46.4.1/
1347
400B_1004 Block Attributes Register (SDHC_BLKATTR) 32 R/W 0000_0000h
46.4.2/
1348
400B_1008 Command Argument Register (SDHC_CMDARG) 32 R/W 0000_0000h
46.4.3/
1349
400B_100C Transfer Type Register (SDHC_XFERTYP) 32 R/W 0000_0000h
46.4.4/
1350
400B_1010 Command Response 0 (SDHC_CMDRSP0) 32 R 0000_0000h
46.4.5/
1354
400B_1014 Command Response 1 (SDHC_CMDRSP1) 32 R 0000_0000h
46.4.6/
1355
400B_1018 Command Response 2 (SDHC_CMDRSP2) 32 R 0000_0000h
46.4.7/
1355
400B_101C Command Response 3 (SDHC_CMDRSP3) 32 R 0000_0000h
46.4.8/
1355
400B_1020 Buffer Data Port Register (SDHC_DATPORT) 32 R/W 0000_0000h
46.4.9/
1357
400B_1024 Present State Register (SDHC_PRSSTAT) 32 R 0000_0000h
46.4.10/
1357
400B_1028 Protocol Control Register (SDHC_PROCTL) 32 R/W 0000_0020h
46.4.11/
1362
400B_102C System Control Register (SDHC_SYSCTL) 32 R/W 0000_8008h
46.4.12/
1366
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1346 Freescale Semiconductor, Inc.