Information

SDHC_PROCTL field descriptions (continued)
Field Description
all these transactions. It is not necessary to change for each transaction. When the software issues
multiple SD commands, setting the bit once before the first command is sufficient: it is not necessary to
reset the bit between commands.
0b LED off
1b LED on
46.4.12 System Control Register (SDHC_SYSCTL)
Address: SDHC_SYSCTL is 400B_1000h base + 2Ch offset = 400B_102Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
INITA
0 0 0
0
DTOCV
W RSTD RSTC RSTA
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SDCLKFS DVS
SDCLKEN
PEREN
HCKEN
IPGEN
W
Reset
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
SDHC_SYSCTL field descriptions
Field Description
31–28
Reserved
This read-only field is reserved and always has the value zero.
27
INITA
Initialization Active
When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks are sent, this bit is self cleared.
This bit is very useful during the card power-up period when 74 SD-clocks are needed and the clock auto
gating feature is enabled. Writing 1 to this bit when this bit is already 1 has no effect. Writing 0 to this bit at
any time has no effect. When either of the PRSSTAT[CIHB] and PRSSTAT[CDIHB] bits are set, writing 1
to this bit is ignored (i.e. when command line or data lines are active, write to this bit is not allowed). On
the otherhand, when this bit is set, i.e., during intialization active period, it is allowed to issue command,
and the command bit stream will appear on the CMD pad after all 80 clock cycles are done. So when this
command ends, the driver can make sure the 80 clock cycles are sent out. This is very useful when the
driver needs send 80 cycles to the card and does not want to wait till this bit is self cleared.
26
RSTD
Software Reset For DAT Line
Only part of the data circuit is reset. DMA circuit is also reset.
The following registers and bits are cleared by this bit:
• Data port register
• Buffer is cleared and initialized.Present State register
• Buffer Read Enable
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1366 Freescale Semiconductor, Inc.