Information

SDHC_SYSCTL field descriptions (continued)
Field Description
Setting 00h bypasses the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
behavior of this prescaler is undefined. The two default divider values can be calculated by the frequency
of SDHC clock and the following divisor bits.
The frequency of SDCLK is set by the following formula: Clock frequency = (Base clock) / (prescaler x
divisor)
For example, if the base clock frequency is 96 MHz, and the target frequency is 25 MHz, then choosing
the prescaler value of 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency less
than or equal to the target. Similarly, to approach a clock value of 400 kHz, the prescaler value of 08h and
divisor value of eh yields the exact clock value of 400 kHz. The reset value of this bit field is 80h, so if the
input base clock (SDHC clock) is about 96 MHz, the default SD clock after reset is 375 kHz.
According to the SD Physical Specification Version 1.1 and the SDIO Card Specification Version 1.2, the
maximum SD clock frequency is 50 MHz and shall never exceed this limit.
Only the following settings are allowed:
01h Base clock divided by 2
02h Base clock divided by 4
04h Base clock divided by 8
08h Base clock divided by 16
10h Base clock divided by 32
20h Base clock divided by 64
40h Base clock divided by 128
80h Base clock divided by 256
7–4
DVS
Divisor
This register is used to provide a more exact divisor to generate the desired SD clock frequency. Note the
divider can even support odd divisor without deterioration of duty cycle.
The setting are as following:
0h Divisor by 1
1h Divisor by 2
...
Eh Divisor by 15
Fh Divisor by 16
3
SDCLKEN
SD Clock Enable
The host controller shall stop SDCLK when writing this bit to 0. SDCLK frequency can be changed when
this bit is 0. Then, the host controller shall maintain the same clock frequency until SDCLK is stopped
(stop at SDCLK = 0). If the IRQSTAT[CINS] is cleared, this bit should be cleared by the host driver to
save power.
2
PEREN
Peripheral Clock Enable
If this bit is set, SDHC clock will always be active and no automatic gating is applied. Thus the SDCLK is
active except for when auto gating-off during buffer danger (buffer about to over-run or under-run). When
this bit is cleared, the SDHC clock will be automatically off whenever there is no transaction on the SD
bus. Since this bit is only a feature enabling bit, clearing this bit does not stop SDCLK immediately.
The SDHC clock will be internally gated off, if none of the following factors are met:
• The cmd part is reset, or
• Data part is reset, or
• A soft reset, or
• The cmd is about to send, or
• Clock divisor is just updated, or
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1368 Freescale Semiconductor, Inc.