Information

SDHC_IRQSTATEN field descriptions (continued)
Field Description
0b Masked
1b Enabled
6
CINSEN
Card Insertion Status Enable
0b Masked
1b Enabled
5
BRRSEN
Buffer Read Ready Status Enable
0b Masked
1b Enabled
4
BWRSEN
Buffer Write Ready Status Enable
0b Masked
1b Enabled
3
DINTSEN
DMA Interrupt Status Enable
0b Masked
1b Enabled
2
BGESEN
Block Gap Event Status Enable
0b Masked
1b Enabled
1
TCSEN
Transfer Complete Status Enable
0b Masked
1b Enabled
0
CCSEN
Command Complete Status Enable
0b Masked
1b Enabled
Chapter 46 Secured digital host controller (SDHC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1377