Information

46.4.15 Interrupt Signal Enable Register (SDHC_IRQSIGEN)
This register is used to select which interrupt status is indicated to the host system as the
interrupt. These status bits all share the same interrupt line. Setting any of these bits to 1
enables interrupt generation. The corresponding status register bit will generate an
interrupt when the corresponding interrupt signal enable bit is set.
Address: SDHC_IRQSIGEN is 400B_1000h base + 38h offset = 400B_1038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
DMAEIEN
0
AC12EIEN
0
DEBEIEN
DCEIEN
DTOEIEN
CIEIEN
CEBEIEN
CCEIEN
CTOEIEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CINTIEN
CRMIEN
CINSIEN
BRRIEN
BWRIEN DINTIEN
BGEIEN
TCIEN
CCIEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_IRQSIGEN field descriptions
Field Description
31–29
Reserved
This read-only field is reserved and always has the value zero.
28
DMAEIEN
DMA Error Interrupt Enable
0b Masked
1b Enabled
27–25
Reserved
This read-only field is reserved and always has the value zero.
24
AC12EIEN
Auto CMD12 Error Interrupt Enable
0b Masked
1b Enabled
23
Reserved
This read-only field is reserved and always has the value zero.
22
DEBEIEN
Data End Bit Error Interrupt Enable
0b Masked
1b Enabled
21
DCEIEN
Data CRC Error Interrupt Enable
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1378 Freescale Semiconductor, Inc.