Information

SDHC_IRQSIGEN field descriptions (continued)
Field Description
0b Masked
1b Enabled
20
DTOEIEN
Data Timeout Error Interrupt Enable
0b Masked
1b Enabled
19
CIEIEN
Command Index Error Interrupt Enable
0b Masked
1b Enabled
18
CEBEIEN
Command End Bit Error Interrupt Enable
0b Masked
1b Enabled
17
CCEIEN
Command CRC Error Interrupt Enable
0b Masked
1b Enabled
16
CTOEIEN
Command Timeout Error Interrupt Enable
0b Masked
1b Enabled
15–9
Reserved
This read-only field is reserved and always has the value zero.
8
CINTIEN
Card Interrupt Enable
0b Masked
1b Enabled
7
CRMIEN
Card Removal Interrupt Enable
0b Masked
1b Enabled
6
CINSIEN
Card Insertion Interrupt Enable
0b Masked
1b Enabled
5
BRRIEN
Buffer Read Ready Interrupt Enable
0b Masked
1b Enabled
4
BWRIEN
Buffer Write Ready Interrupt Enable
0b Masked
1b Enabled
3
DINTIEN
DMA Interrupt Enable
Table continues on the next page...
Chapter 46 Secured digital host controller (SDHC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1379