Information

46.4.17 Host Controller Capabilities (SDHC_HTCAPBLT)
This register provides the host driver with information specific to the SDHC
implementation. The value in this register is the power-on-reset value, and does not
change with a software reset. Any write to this register is ignored.
Address: SDHC_HTCAPBLT is 400B_1000h base + 40h offset = 400B_1040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
VS18 VS30 VS33
SRS
DMAS
HSS
ADMAS
0 MBL
W
Reset
0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_HTCAPBLT field descriptions
Field Description
31–27
Reserved
This read-only field is reserved and always has the value zero.
26
VS18
Voltage Support 1.8 V
This bit shall depend on the host system ability.
0b 1.8 V not supported
1b 1.8 V supported
25
VS30
Voltage Support 3.0 V
This bit shall depend on the host system ability.
0b 3.0 V not supported
1b 3.0 V supported
24
VS33
Voltage Support 3.3 V
This bit shall depend on the host system ability.
0b 3.3 V not supported
1b 3.3 V supported
Table continues on the next page...
Chapter 46 Secured digital host controller (SDHC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1383