Information

SDHC_HTCAPBLT field descriptions (continued)
Field Description
23
SRS
Suspend/Resume Support
This bit indicates whether the SDHC supports suspend / resume functionality. If this bit is 0, the suspend
and resume mechanism, as well as the read Wwait, are not supported, and the host driver shall not issue
either suspend or resume commands.
0b Not supported
1b Supported
22
DMAS
DMA Support
This bit indicates whether the SDHC is capable of using the internal DMA to transfer data between system
memory and the data buffer directly.
0b DMA not supported
1b DMA supported
21
HSS
High Speed Support
This bit indicates whether the SDHC supports high speed mode and the host system can supply a SD
Clock frequency from 25 MHz to 50 MHz.
0b High speed not supported
1b High speed supported
20
ADMAS
ADMA Support
This bit indicates whether the SDHC supports the ADMA feature.
0b Advanced DMA not supported
1b Advanced DMA supported
19
Reserved
This read-only field is reserved and always has the value zero.
18–16
MBL
Max Block Length
This value indicates the maximum block size that the host driver can read and write to the buffer in the
SDHC. The buffer shall transfer block size without wait cycles.
000b 512 bytes
001b 1024 bytes
010b 2048 bytes
011b 4096 bytes
15–0
Reserved
This read-only field is reserved and always has the value zero.
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1384 Freescale Semiconductor, Inc.