Information

Forcing a card interrupt will generate a short pulse on the DAT[1] line, and the driver
may treat this interrupt as a normal interrupt. The interrupt service routine may skip
polling the card interrupt factor as the interrupt is self cleared.
Address: SDHC_FEVT is 400B_1000h base + 50h offset = 400B_1050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
0
0
0 0 0 0 0 0 0
W
CINT
0
DMAE
0
AC12E
0
DEBE
DCE
DTOE
CIE
CEBE
CCE
CTOE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
0 0 0
0
0
W
0
CNIBAC12E
0
AC12IE
AC12EBE
AC12CE
AC12TOE
AC12NE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_FEVT field descriptions
Field Description
31
CINT
Force Event Card Interrupt
Writing 1 to this bit generates a short low-level pulse on the internal DAT[1] line, as if a self clearing
interrupt was received from the external card. If enabled, the CINT bit will be set and the interrupt service
routine may treat this interrupt as a normal interrupt from the external card.
30–29
Reserved
This field is reserved.
28
DMAE
Force Event DMA Error
Forces the DMAE bit of Interrupt Status Register to be set.
27–25
Reserved
This field is reserved.
24
AC12E
Force Event Auto Command 12 Error
Forces the IRQSTAT[AC12E] to be set.
23
Reserved
This field is reserved.
22
DEBE
Force Event Data End Bit Error
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1386 Freescale Semiconductor, Inc.