Information

CM D 53CM D 53
SDIO Data
block #1
SDIO Data
block #1
Data
64 bytes
Data
64 bytes
Data
32 bytes
SDIO Data
32 bytes
SDIO Data
32 bytes
Data
64 bytes
SDIO Data
block #2
SDIO Data
block #2
E ight 64 byt e block s ar e sent in B lock tr ansfer m ode and the r em ainder
32 bytes ar e sent in B yte T r ansfer m ode
WLAN Frame is divided equally into 64 byte blocks plus the remainder 32 bytes
544 Bytes WLAN Frame
SDIO Data
block #8
SDIO Data
block #8
CM D 53
Frame Body
ICV
FCS
IV
802.
.
11
MAC
header
Figure 46-30. Example for dividing large data transfers
46.5.1.5 External DMA request
When the internal DMA is not in use, and external DMA request is enabled, the data
buffer will generate a DMA request to the system. During a write operation, when the
number of WRWML words can be held in the buffer free space, a DMA request is sent ,
informing the host system of a DMA write. The IRQSTAT[BWR] bit is also set, as long
as the IRQSTATEN[BWRSEN] bit is set. The DMA request is immediately de-asserted
when an access to the DATPORT register is made. If the buffer's free space still meets
the watermark condition, the DMA request is asserted again after a cycle.
On read operation, when the number of RDWML words are already in the buffer, a DMA
request is sent , informing the host system for a DMA read. The IRQSTAT[BRR] bit is
also set, as long as the IRQSTATEN[BRRSEN] bit is set. The DMA request is
immediately de-asserted when an access to the DATPORT register is made. If the
buffer's data still meets the watermark condition, the DMA request is asserted again after
a cycle.
Chapter 46 Secured digital host controller (SDHC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1399