Information

Table 46-36. Format of the ADMA2 descriptor table (continued)
Valid Valid = 1 indicates this line of descriptor is effective. If valid = 0 generate ADMA error interrupt and
stop ADMA.
End End = 1 indicates current descriptor is the ending one.
Int Int = 1 generates DMA interrupt when this descriptor is done.
System Address Register points to
the head node of Descriptor Table
System Address Register
Advanced DMA
System Memory
Address
Address3
Attribute
Tran, End
Address
Length
Attribute
Tran
Link
Length1
Length2
Address1
Address2
Data Length (invisible)
Data Address (invisible)
Flags
State
Machine
SDMA
ADMA Error
Page Data
Descriptor Table
Page Data
Transfer Complete
DMA Interrupt
Figure 46-33. Concept and access method of ADMA2 descriptor table
46.5.2.4.2 ADMA interrupt
If the 'interrupt' flag of descriptor is set, ADMA will generate an interrupt according to
different type descriptor:
For ADMA1:
• Set type descriptor: interrupt is generated when data length is set.
• Tran type descriptor: interrupt is generated when this transfer is complete.
• Link type descriptor: interrupt is generated when new descriptor address is set.
• Nop type descriptor: interrupt is generated just after this descriptor is fetched.
For ADMA2:
• Tran type descriptor: interrupt is generated when this transfer is complete.
• Link type descriptor: interrupt is generated when new descriptor address is set.
• Nop/Rsv type descriptor: interrupt is generated just after fetch this descriptor.
Chapter 46 Secured digital host controller (SDHC)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1405