Information

• Core/system clock

• MCGPLLCLK or MCGFLLCLK

• EXTAL

• Bypass clock from off-chip (SDHC0_CLKIN)

3.9.5.2 SD bus pullup/pulldown constraints

The SD standard requires the SD bus signals (except the SD clock) to be pulled up during

data transfers. The SDHC also provides a feature of detecting card insertion/removal, by

detecting voltage level changes on DAT[3] of the SD bus. To support this DAT[3] must

be pulled down. To avoid a situation where the SDHC detects voltage changes due to

normal data transfers on the SD bus as card insertion/removal, the interrupt relating to

this event must be disabled after the card has been inserted and detected. It can be re-

enabled after the card is removed.

3.9.6 I

S configuration

This section summarizes how the module has been configured in the chip. For a

comprehensive description of the module itself, see the module’s dedicated chapter.

Signal multiplexing

access

Peripheral

bridge

Module signals

I S

Figure 3-54. I

S configuration

Table 3-69. Reference links to related information

Topic Related module Reference

Full description I

S I2S

System memory map System memory map

Clocking Clock Distribution

Power management Power management

Signal multiplexing Port control Signal Multiplexing

Communication interfaces

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

142 Freescale Semiconductor, Inc.