Information

47.1.1 Block diagram
The following figure illustrates the organization of the I
2
S. It consists of control registers
to set up the port, status register, separate transmit and receive circuits with FIFO
registers, and separate serial clock and frame sync generation for the transmit and receive
sections. The second set of Tx and Rx FIFOs replicates the logic used for the first set of
FIFOs.
Transmit Clock
Control Reg
RCR
Peripheral Bus
STXD
SRXD
STCK
STFS
SRCK/SYS_CLK
SRFS
Tx Clock
Generator
Tx Sync
Generator
Tx and RX
Rx Clock
Generator
Rx Sync
Generator
Control Reg
CR
Tx and Rx FIFO
and shift register logic
Control
TCR
TCCR
32-bit
RCCR
Receive Clock
Control Reg
Transmit
Config Reg
Receive
Config Reg
Figure 47-1. Customer-facing I
2
S block diagram
47.1.2 Features
The I
2
S includes the following features:
• Independent (asynchronous) or shared (synchronous) transmit and receive sections
with separate or shared internal/external clocks and frame syncs, operating in master
or slave mode.
• Normal mode operation using frame sync
Introduction
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1450 Freescale Semiconductor, Inc.