Information

• Network mode operation allowing multiple devices to share the port with as many as
thirty-two time slots
• Gated clock mode operation requiring no frame sync
• 2 sets of transmit and receive FIFOs. Each of the four FIFOs is 15x32 bits. The two
sets of Tx/Rx FIFOs can be used in network mode to provide 2 independent channels
for transmission and reception
• Programmable data interface modes such as I
2
S, lsb- and msb-aligned
• Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)
• Program options for frame sync and clock generation
• Programmable I
2
S modes (master, slave or normal). Oversampling clock available as
output from SRCK in I
2
S master mode
• AC97 support
• Completely separate clock and frame sync selections for the receive and transmit
sections. In the AC97 standard, the clock is taken from an external source and frame
sync is generated internally.
• External network clock input for I
2
S master mode. Programmable oversampling
clock of the sampling frequency available as output in master mode at SRCK, when
operated in synchronous mode.
• Programmable internal clock divider
• Transmit and receive time slot mask registers for reduced CPU overhead
• I
2
S power-down feature
47.1.3 Modes of operation
I
2
S has the following basic operating modes.
• Normal mode
• Asynchronous protocol
• Synchronous protocol
• Network mode
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1451