Information

I2S
I2S
STXD
SRXD
STCK
STFS
SRCK
SRFS
I2S
STXD
SRXD
STCKSTCK
STFS
SRCK
SRFS
I2S
STXD
SRXD
STCK
STFS
SRCK
SRFS
STXD
SRXD
STCK
STFS
SRCK
SRFS
I2S internal continuous clock for TX/RX (RCR[RXDIR] = 1,TCR[TXDIR] = 1,
RCR[RFDIR] = 1,TCR[TFDIR] = 1, CR[SYN] = 0)
I2S external continuous clock for TX/RX (RCR[RXDIR] = 0,TCR[TXDIR] = 0,
RCR[RFDIR] = 0,TCR[TFDIR] = 0, CR[SYN] = 0)
I2S internal continuous clock for RX (RCR[RXDIR] = 1, TCR[TXDIR] = 0,
RCR[RFDIR] = 1,TCR[TFDIR] = 0, CR[SYN] = 0)
I2S external continuous clock for TX
I2S internal continuous clock for TX (RCR[RXDIR] = 0, TCR[TXDIR] = 1,
RCR[RFDIR] = 0, TCR[TFDIR] = 1, CR[SYN] = 0)
I2S external continuous clock for RX
Figure 47-2. Asynchronous (SYN = 0) I
2
S configurations—continuous clock
The following figure shows an example of the port signals for an 8-bit data transfer.
Continuous and gated clock signals are shown, as well as the bit-length frame sync signal
and the word-length frame sync signal.
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1455