Information

Table 47-3. Clock pin configurations (continued)
CR
[SYN]
RCR TCR
SRCK STCK SRFS STFS
RXDIR RFDIR TXDIR TFDIR
0 1 0 1 0 RCK out TCK out RFS in TFS in
0 1 0 1 1 RCK out TCK out RFS in TFS out
0 1 1 1 0 RCK out TCK out RFS out TFS in
0 1 1 1 1 RCK out TCK out RFS out TFS out
Synchronous mode
1 0 x 0 0 — CK in — FS in
1 0 x 0 1 — CK in — FS out
1 0 x 1 0 — CK out — FS in
1 0 x 1 1 — CK out — FS out
1 1 x 0 x — Gated in — —
1 1 x 1 x — Gated out — —
47.3 Memory map/register definition
This section consists of register descriptions in address order. Each description includes a
standard register diagram with an associated figure number. Details of register bit and
field function follow the register diagrams in bit order.
I2S memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_F000 I2S Transmit Data Registers 0 (I2S0_TX0) 32 R/W 0000_0000h
47.3.1/
1459
4002_F004 I2S Transmit Data Registers 1 (I2S0_TX1) 32 R/W 0000_0000h
47.3.2/
1459
4002_F008 I2S Receive Data Registers 0 (I2S0_RX0) 32 R 0000_0000h
47.3.3/
1460
4002_F00C I2S Receive Data Registers 1 (I2S0_RX1) 32 R 0000_0000h
47.3.4/
1460
4002_F010 I2S Control Register (I2S0_CR) 32 R/W 0000_0000h
47.3.5/
1461
4002_F014 I2S Interrupt Status Register (I2S0_ISR) 32 R/W 0000_3003h
47.3.6/
1464
Table continues on the next page...
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1457