Information

I2S memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_F018 I2S Interrupt Enable Register (I2S0_IER) 32 R/W 0000_3003h
47.3.7/
1469
4002_F01C I2S Transmit Configuration Register (I2S0_TCR) 32 R/W 0000_0200h
47.3.8/
1473
4002_F020 I2S Receive Configuration Register (I2S0_RCR) 32 R/W 0000_0200h
47.3.9/
1475
4002_F024 I2S Transmit Clock Control Registers (I2S0_TCCR) 32 R/W 0004_0000h
47.3.10/
1477
4002_F028 I2S Receive Clock Control Registers (I2S0_RCCR) 32 R/W 0004_0000h
47.3.11/
1479
4002_F02C I2S FIFO Control/Status Register (I2S0_FCSR) 32 R/W 0081_0081h
47.3.12/
1480
4002_F038 I2S AC97 Control Register (I2S0_ACNT) 32 R/W 0000_0000h
47.3.13/
1486
4002_F03C I2S AC97 Command Address Register (I2S0_ACADD) 32 R/W 0000_0000h
47.3.14/
1487
4002_F040 I2S AC97 Command Data Register (I2S0_ACDAT) 32 R/W 0000_0000h
47.3.15/
1488
4002_F044 I2S AC97 Tag Register (I2S0_ATAG) 32 R/W 0000_0000h
47.3.16/
1488
4002_F048 I2S Transmit Time Slot Mask Register (I2S0_TMSK) 32 R/W 0000_0000h
47.3.17/
1489
4002_F04C I2S Receive Time Slot Mask Register (I2S0_RMSK) 32 R/W 0000_0000h
47.3.18/
1489
4002_F050 I2S AC97 Channel Status Register (I2S0_ACCST) 32 R 0000_0000h
47.3.19/
1490
4002_F054 I2S AC97 Channel Enable Register (I2S0_ACCEN) 32
W
(always
reads
zero)
0000_0000h
47.3.20/
1490
4002_F058 I2S AC97 Channel Disable Register (I2S0_ACCDIS) 32
W
(always
reads
zero)
0000_0000h
47.3.21/
1491
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1458 Freescale Semiconductor, Inc.