Information

I2Sx_CR field descriptions (continued)
Field Description
This bit provides the option to keep the frame-sync and clock enabled or to disable them after the receive
frame in which the receiver is disabled. Writing to this bit has effect only when CR[RE] is disabled.The
receiver is disabled by clearing the CR[RE] bit.
0 Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This may
be required when Frame-sync and Clocks are required from I
2
S, even when no data is to be received.
1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where
receiver is already disabled in current or previous frames.
10
TFRCLKDIS
Transmit Frame Clock Disable.
This bit provide option to keep the frame-sync and clock enabled or disabled after current transmit frame,
in which transmitter is disabled by clearing CR[TE] bit. Writing to this bit has effect only when I
2
S is
enabled CR[TE] is disabled.
0 Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This may
be required when frame-sync and clocks are required from I
2
S, even when no data is to be received.
1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case where
transmitter is already disabled in current or previous frames.
9
CLKIST
Clock Idle State.
This bit controls the idle state of the transmit clock port during I
2
S internal gated mode. Note: When Clock
idle state is `1' the clock polarity should always be negedge triggered and when clock idle = `0' the clock
polarity should always be positive edge triggered.
0 Clock idle state is `0'.
1 Clock idle state is `1'.
8
TCHEN
Two-Channel Operation Enable.
This bit allows I
2
S to operate in the two-channel mode.In this mode while receiving, the RXSR transfers
data to RX0 and RX1 alternately and while transmitting, data is alternately transferred from TX0 and TX1
to TXSR. For an even number of slots, two-channel operation can be enabled to optimize usage of both
FIFOs or disabled as in the case of odd number of active slots. This feature is especially useful in I2S
mode, where data for left speaker can be placed in Tx-FIFO0 and for right speaker in Tx-FIFO1.
0 Two-channel mode disabled.
1 Two-channel mode enabled.
7
SYSCLKEN
System Clock (Oversampling Clock) Enable.
When set, this bit allows the I
2
S to output the (network clock) at the SRCK port, provided that
synchronous mode, and transmit internal clock mode are set. The relationship between bit clock and
network clock is determined by DIV2, PSR, and PM bits. This feature is especially useful in I2S master
mode to output oversampling clock on SRCK port.
0 Network clock not output on SRCK port.
1 Network clock output on SRCK port.
6–5
I2SMODE
I2S Mode Select
These bits allow the I
2
S to operate in normal, I
2
S master or I
2
S slave mode.
00 Normal mode
01 I
2
S master mode
Table continues on the next page...
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1462 Freescale Semiconductor, Inc.