Information

I2Sx_CR field descriptions (continued)
Field Description
10 I
2
S slave mode
11 Normal mode
4
SYN
Synchronous Mode.
This bit controls whether I
2
S is in synchronous mode or not. In synchronous mode, the transmit and
receive sections of I
2
S share a common clock port (STCK) and frame sync port (STFS).
0 Asynchronous mode selected.
1 Synchronous mode selected.
3
NET
Network Mode.
This bit controls whether I
2
S is in network mode or not.
0 Network mode not selected.
1 Network mode selected.
2
RE
Receive Enable.
Enables the receive section of the I
2
S. When this bit is enabled, data reception starts with the arrival of
the next frame sync. If data is being received when this bit is cleared, data reception continues until the
end of the current frame and then stops. If this bit is set again before the second to last bit of the last time
slot in the current frame, then reception continues without interruption. CR[RE] should not be toggled in
the same frame.
0 Receive section disabled.
1 Receive section enabled.
1
TE
Transmit Enable.
This control bit enables the transmit section of the I
2
S. It enables the transfer of the contents of the TX
registers to the TXSR and also enables the internal transmit clock. The transmit section is enabled when
this bit is set and a frame boundary is detected. When this bit is cleared, the transmitter continues to send
data until the end of the current frame and then stops. Data can be written to the TX registers with the
CR[TE] bit cleared (the corresponding TDE bit will be cleared). If the CR[TE] bit is cleared and then set
again before the second to last bit of the last time slot in the current frame, data transmission continues
without interruption. The normal transmit enable sequence is to write data to the TX register(s) and then
set the CR[TE] bit. The normal disable sequence is to clear the CR[TE] and IER[TIE] bits after the TDE bit
is set.
In gated clock mode, clearing the CR[TE] bit results in the clock stopping after the data currently in TXSR
has shifted out. When the CR[TE] bit is set, the clock starts immediately (for internal gated clock mode).
CR[TE] should not be toggled in the same frame.
After enabling/disabling transmission, I
2
S expects 4 setup clock cycles before arrival of frame-sync for
frame-sync to be accepted by I
2
S. In case of fewer clock cycles, there is high probability of the frame-sync
to get missed.
NOTE: If continuos clock is not provided, I
2
S expects 6 clock cycles before arrival of frame-sync for
frame-sync to be accepted by I
2
S.
0 Transmit section disabled.
1 Transmit section enabled.
0
I2SEN
I2S Enable.
Table continues on the next page...
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1463