Information

I2Sx_ISR field descriptions (continued)
Field Description
0
TFE0
Transmit FIFO Empty 0.
This flag is set when the empty slots in Tx FIFO exceed or are equal to the selected Tx FIFO WaterMark
0 (TFWM0) threshold. The setting of TFE0 only causes an interrupt when IER[TIE] and IER[TFE0EN] are
set and Tx FIFO0 is enabled. The TFE0 bit is automatically cleared when the data level in Tx FIFO0
becomes more than the amount specified by the watermark bits. The TFE0 bit is set by POR and I
2
S
reset.
0 Transmit FIFO0 has data for transmission.
1 Transmit FIFO0 is empty.
47.3.7 I
2
S Interrupt Enable Register (I2Sx_IER)
The I2S interrupt enable register (IER) is a 25-bit register used to set up the I2S interrupts
and DMA requests.
Addresses: I2S0_IER is 4002_F000h base + 18h offset = 4002_F018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
RFRC_EN
TFRC_EN
RDMAE
RIE
TDMAE
TIE
CMDAUEN
CMDDUEN
RXTEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RDR1EN RDR0EN
TDE1EN TDE0EN
ROE1EN ROE0EN
TUE1EN TUE0EN
TFSEN
RFSEN
TLSEN
RLSEN
RFF1EN RFF0EN
TFE1EN TFE0EN
W
Reset
0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1
I2Sx_IER field descriptions
Field Description
31–25
Reserved
This read-only field is reserved and always has the value zero.
24
RFRC_EN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
23
TFRC_EN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
Table continues on the next page...
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1469