Information

I2Sx_IER field descriptions (continued)
Field Description
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
6
RFSEN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
5
TLSEN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
4
RLSEN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
3
RFF1EN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
2
RFF0EN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
1
TFE1EN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
0
TFE0EN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
Memory map/register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1472 Freescale Semiconductor, Inc.