Information

47.3.9 I
2
S Receive Configuration Register (I2Sx_RCR)
RCR directs the receive operation of the I2S. A power-on reset clears all RCR bits.
However, I2S reset does not affect the RCR bits.
Addresses: I2S0_RCR is 4002_F000h base + 20h offset = 4002_F020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RXEXT
RXBIT0
RFEN1 RFEN0
RFDIR
RXDIR
RSHFD RSCKP
RFSI
RFSL
REFS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
I2Sx_RCR field descriptions
Field Description
31–11
Reserved
This read-only field is reserved and always has the value zero.
10
RXEXT
Receive Data Extension.
This control bit allows I
2
S to store the received data word in sign extended form. This bit affects data
storage only in case received data is LSB aligned (RCR[9]=1)
0 Sign extension turned off.
1 Sign extension turned on.
9
RXBIT0
Receive Bit 0.
This control bit allows I
2
S to receive the data word at bit position 0 or 15/31 in the receive shift register.
The shifting data direction can be MSB or LSB first, controlled by the RSHFD bit.
0 Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or
12) of receive shift register (MSB aligned).
1 Shifting with respect to bit 0 of receive shift register (LSB aligned).
8
RFEN1
Receive FIFO Enable 1.
This bit enables receive FIFO 1. When enabled, the FIFO allows 15 samples to be received by the I
2
S per
channel (a 16th sample can be shifting in) before RDR1 bit is set. When the FIFO is disabled, an interrupt
is generated when a single sample is received by the I
2
S (provided the interrupt is enabled).
0 Receive FIFO 1 disabled.
1 Receive FIFO 1 enabled.
7
RFEN0
Receive FIFO Enable 0.
This bit enables receive FIFO 0. When enabled, the FIFO allows 15 samples to be received by the I
2
S
(per channel) (a 16th sample can be shifting in) before RDR0 bit is set. When the FIFO is disabled, an
interrupt is generated when a single sample is received by the I
2
S (provided the interrupt is enabled).
0 Receive FIFO 0 disabled.
1 Receive FIFO 0 enabled.
6
RFDIR
Receive Frame Direction.
Table continues on the next page...
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1475