Information

I2Sx_ACNT field descriptions (continued)
Field Description
This bit specifies whether the next frame will carry an AC97 Write Command or not. The programmer
should take care that only one of the bits (WR or RD) is set at a time. When this bit is set, the
corresponding tag bits (corresponding to Command Address and Command Data slots of the next Tx
frame) are automatically set. This bit is automatically cleared by the I
2
S after completing transmission of a
frame.
0 Next frame will not have a Write Command.
1 Next frame will have a Write Command.
3
RD
Read Command.
This bit specifies whether the next frame will carry an AC97 Read Command or not. The programmer
should take care that only one of the bits (WR or RD) is set at a time. When this bit is set, the
corresponding tag bit (corresponding to Command Address slot of the next Tx frame) is automatically set.
This bit is automatically cleared by the I
2
S after completing transmission of a frame.
0 Next frame will not have a Read Command.
1 Next frame will have a Read Command.
2
TIF
Tag in FIFO.
This bit controls the destination of the information received in AC97 tag slot (Slot #0).
0 Tag info stored in ATAG register.
1 Tag info stored in ATAG register and Rx FIFO 0.
1
FV
Fixed/Variable Operation.
This bit selects whether the I
2
S is in AC97 Fixed mode or AC97 Variable mode.
0 AC97 Fixed Mode
1 AC97 Variable Mode.
0
AC97EN
AC97 Mode Enable.
This bit is used to enable I
2
S AC97 operation.
0 AC97 mode disabled.
1 I
2
S in AC97 mode.
47.3.14 I
2
S AC97 Command Address Register (I2Sx_ACADD)
Addresses: I2S0_ACADD is 4002_F000h base + 3Ch offset = 4002_F03Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ACADD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1487