Information

Chapter 4
Memory Map
4.1 Introduction
This device contains various memories and memory-mapped peripherals which are
located in one 32-bit contiguous memory space. This chapter describes the memory and
peripheral locations within that memory space.
4.2 System memory map
The following table shows the high-level device memory map.
Table 4-1. System memory map
System 32-bit Address Range Destination Slave Access
0x0000_0000–0x0FFF_FFFF Program flash and read-only data
(Includes exception vectors in first 1024 bytes)
All masters
0x1000_0000–0x13FF_FFFF • For MK10DX128ZVLQ10: FlexNVM
• For MK10DX128ZVMD10: FlexNVM
• For MK10DX256ZVLQ10: FlexNVM
• For MK10DX256ZVMD10: FlexNVM
• For MK10DN512ZVLQ10: Reserved
• For MK10DN512ZVMD10: Reserved
All masters
0x1400_0000–0x17FF_FFFF For devices with FlexNVM: FlexRAM
For devices with program flash only: Programming
acceleration RAM
All masters
0x1800_0000–0x1FFF_FFFF SRAM_L: Lower SRAM (ICODE/DCODE) All masters
0x2000_0000–0x200F_FFFF SRAM_U: Upper SRAM bitband region All masters
0x2010_0000–0x21FF_FFFF Reserved –
0x2200_0000–0x23FF_FFFF Aliased to SRAM_U bitband Cortex-M4 core
only
0x2400_0000–0x3FFF_FFFF Reserved –
Table continues on the next page...
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 149