Information

I2Sx_ACCEN field descriptions
Field Description
31–10
Reserved
This read-only field is reserved and always has the value zero.
9–0
ACCEN
AC97 Channel Enable.
The Core writes a `1' to these bits to enable an AC97 data channel. Writing a `0' has no effect. Bit [0]
corresponds to the first data slot in an AC97 frame (Slot #3) and Bit [9] corresponds to the tenth data slot
(slot #12). Writes to these bits only have effect in the AC97 Variable mode of operation. These bits are
always read as `0' by the Core.
0 Write has no effect.
1 Write enables the corresponding data channel.
47.3.21 I
2
S AC97 Channel Disable Register (I2Sx_ACCDIS)
Addresses: I2S0_ACCDIS is 4002_F000h base + 58h offset = 4002_F058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
W
ACCDIS
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_ACCDIS field descriptions
Field Description
31–10
Reserved
This read-only field is reserved and always has the value zero.
9–0
ACCDIS
AC97 Channel Disable.
The Core writes a `1' to these bits to disable an AC97 data channel. Writing a `0' has no effect. Bit [0]
corresponds to the first data slot in an AC97 frame (Slot #3) and Bit [9] corresponds to the tenth data slot
(slot #12). Writes to these bits only have effect in the AC97 Variable mode of operation. These bits are
always read as `0' by the Core.
0 Write has no effect.
1 Write disables the corresponding data channel.
47.4 Functional description
This section provides the functional details of the I
2
S module.
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1491