Information

• In gated-external mode, the data word in transmitted on the external clock.

• In gated-internal mode, the data word is transmitted whenever data is available in the

transmit FIFO.

If transmit FIFO 0 is not enabled and the transmit data register empty enable

(IER[TDE0EN]) and transmit interrupt enable (IER[TIE]) bits are set, transmit interrupt 0

occurs when the word in I

S_TX0 is shifted to transmit shift (TXSR) register.

If transmit FIFO 0 is enabled and the transmit FIFO full enable (IER[TFF0EN]) and

transmit interrupt enable (IER[TIE]) bits are set, transmit interrupt 0 occurs when the

number of empty slots in transmit FIFO 0 are equal to or exceed the selected threshold

value (transmit FIFO 0 watermark (FCSR[TFWM0]). If transmit FIFO 0 is enabled and

filled with data, 15 data words can be transferred before the core must write new data to

the TX0 register.

The STXD port is disabled except during the data transmission period. For a continuous

clock, the optional frame sync output and clock outputs are not disabled, even if the

receiver and transmitter are disabled.

47.4.1.1.2 Normal mode receive

The conditions for data reception from the I

S are:

1. I

S enabled (CR[I2SEN] = 1)

2. Enable receive FIFO (optional)

3. Receiver enabled (CR[RE] = 1)

4. Frame sync active (for continuous clock case)

5. Bit clock begins (for gated clock case)

With the above conditions in normal mode with a continuous clock, each time the frame

sync signal is generated (or detected) a data word is clocked in. With the above

conditions and a gated clock, each time the clock begins, a data word is clocked in.

If receive FIFO 0 is not enabled and receive interrupt enable (IER[RIE]) and received

data 0 ready enable (IER[RDR0EN]) bits are set, receive interrupt 0 occurs when

received data word is transferred from the receive shift register (RXSR) to the receive

data register 0 (RX0), thus setting the receive data ready 0 (RDR0) flag.

Chapter 47 Integrated interchip sound (I2S)

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 1493