Information

Note
A pull-down resistor is required in the gated clock mode,
because the clock port is disabled between transmissions.
The Tx data register is loaded with the data to be transmitted. On arrival of the clock, this
data is transferred to the transmit shift register which gets transmitted on the STXD
output. Simultaneously, the receive shift register shifts in the received data available on
the SRXD input and at the end of the time slot, this data is transferred to the Rx data
register. In internal gated clock mode, the Tx data line and clock output port are put in the
high-impedance state at the end of transmission of the last bit (at the completion of the
complete clock cycle). Whereas, in external gated clock mode, the Tx data line is tri-
stated at the last inactive edge of the incoming bit clock (during the last bit in a data
word).
Gated
CLK
TX
DATA
STXD
RX
DATA
SRXD
Figure 47-47. Normal mode timing - internal gated clock
The following figure shows a case for external (I
2
S receives clock) gated clock mode
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1495