Information

Section Number Title Page
18.3 Memory Map/Register Definition.................................................................................................................................363
18.3.1 Control/Error Status Register (MPU_CESR)..............................................................................................366
18.3.2 Error Address Register, Slave Port n (MPU_EARn)...................................................................................368
18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)......................................................................................369
18.3.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0)..............................................................................370
18.3.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1)..............................................................................371
18.3.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2)..............................................................................371
18.3.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3)..............................................................................374
18.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................375
18.4 Functional Description..................................................................................................................................................377
18.4.1 Access Evaluation Macro.............................................................................................................................377
18.4.2 Putting It All Together and Error Terminations...........................................................................................378
18.4.3 Power Management......................................................................................................................................379
18.5 Initialization Information..............................................................................................................................................379
18.6 Application Information................................................................................................................................................379
Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Introduction...................................................................................................................................................................383
19.1.1 Features........................................................................................................................................................383
19.1.2 General operation.........................................................................................................................................383
19.2 Memory map/register definition...................................................................................................................................384
19.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................385
19.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................389
19.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................394
19.3 Functional Description..................................................................................................................................................399
19.3.1 Access support.............................................................................................................................................399
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 15