Information

CLK
FS
TX
DATA
TDE
TUE
SRXD
ROE
RDR
REG
RX
DATA
0x7B
0x7B
0x12 0x34
0xD6
0x55
0x5E
0xD6
0x5E0x55
0x5E
0x5E
0xD6
0xD6
0x5E
0x12
$7B
0xD6
0xD6
STXD
REG
Note: Processor must write ‘1’ to the corresponding TUE/ROE Interrupt status bit in ISR to clear TUE/ROE Interrupt
Figure 47-49. Network mode timing - continuous clock
47.4.1.3 Gated clock mode
Gated clock mode often connects to SPI-type interfaces on microcontroller units (MCUs)
or external peripheral devices. In gated clock mode, the presence of the clock indicates
that valid data is on the STXD or SRXD signals. For this reason, no frame sync is needed
in this mode. After transmission of data completes, the clock is pulled to the inactive
state. Gated clocks are allowed for the transmit and receive sections with either internal
or external clock in normal mode. Gated clocks are not allowed in network mode. See
Table 47-3 for I
2
S configuration for gated-mode operation.
The clock operates when the CR[TE] bit and/or the CR[RE] bit are appropriately enabled.
For the case of internally generated clock, all internal bit clocks, word clocks, and frame
clocks continue to operate. When a valid time slot occurs (such as the first time slot in
Functional description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1500 Freescale Semiconductor, Inc.