Information

normal mode), the internal bit clock is enabled onto the appropriate clock port. This
allows data to be transferred out in periodic intervals in gated clock mode. With an
external clock, the I
2
S module waits for a clock signal to be received. After the clock
begins, valid data is shifted in. Ensure all RCCR[DC] bits are cleared when the module is
used in gated mode. In gated mode the ISR[TFS], ISR[RFS], ISR[TLS], ISR[RLS],
ISR[TRFC] and ISR[RFRC] bits are not generated.
For gated clock operated in external clock mode, proper clock signalling must apply to
the I
2
S STCK for it to function properly. When TCR[TSCKP] is cleared, CR[CLKIST]
must be set. When TCR[TSCKP] is set, CR[CLKIST] value must be cleared. If the I
2
S
uses rising edge transition to clock data (TCR[TSCKP] = 0) and the falling edge
transition to latch data (RCR[RSCKP] = 0), the clock must be in an active low state when
idle. If the I
2
S uses falling edge transition to clock data (TCR[TSCKP] = 1) and the rising
edge transition to latch data (RCR[RSCKP] = 1), the clock must be in a active high state
when idle. The following diagrams illustrate the different edge clocking/latching.
STCK
STXD
SRXD
TCR[TSCKP] = 0, RCR[RSCKP] = 0
Figure 47-50. Internal gated mode timing - rising edge clocking/falling edge latching
STCK
STXD
SRXD
TCR[TSCKP] = 1, RCR[RSCKP] = 1
Figure 47-51. Internal gated mode timing - falling edge clocking/rising edge latching
STCK
STXD
SRXD
TCR[TSCKP] = 0, RCR[RSCKP] = 0
Figure 47-52. External gated mode timing - rising edge clocking/falling edge latching
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1501