Information

TCR[TSCKP] = 1, RCR[RSCKP] = 1
STCK
STXD
SRXD
Figure 47-53. External gated mode timing - falling edge clocking/rising edge latching
Note
• The bit clock signals must not have timing glitches. If a
single glitch occurs, all ensuing transfers are out of
synchronization.
• In external gated mode, even though the transmit data line
is tri-stated at the last non-active edge of the bit clock, the
round trip delay should sufficiently take care of hold time
requirements at the external receiver.
47.4.1.4 I
2
S mode
The I
2
S is compliant to the Inter-IC Sound (I
2
S) bus specification from Philips
Semiconductors (February 1986, Revised June 5, 1996). The following figure depicts
basic I
2
S protocol timing.
Word (n-1)
Right channel
Word (n+1)
Right channel
Word (n)
Left channel
msb
lsb msb
Serial data
Frame sync
Serial clock
Figure 47-54. I
2
S mode timing - serial clock, frame sync and serial data
Select I
2
S mode using the options listed in the following table.
Table 47-50. I
2
S mode selection
CR[I2SMODE] Mode type
00 Normal mode
01 I
2
S master mode
Table continues on the next page...
Functional description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1502 Freescale Semiconductor, Inc.