Information

• Rx frame sync length set to one-word-long-frame (RCR[RFSL]=0)
• Tx shifting w.r.t. bit 0 of TXSR (TCR[TXBIT0] = 1)
• Rx shifting w.r.t. bit 0 of RXSR (RCR[RXBIT0] = 1)
Set the TCCR[PM, PSR, DIV2, WL, DC] to configure the bit clock and frame sync.
The word length is fixed to 32 in I
2
S master mode and the RCCR[WL] bits determine the
number of bits that contain valid data (out of the 32 transmitted/received bits in each
channel).
47.4.1.4.2 I
2
S slave mode
In I
2
S slave mode (CR[I2SMODE] = 10b), the following additional settings are
recommended:
• External generated bit clock (TCR[TXDIR] = 0)
• External generated frame sync (TCR[TFDIR] = 0)
The processor automatically performs these settings in I
2
S slave mode:
• Normal mode is selected (CR[NET] = 0)
• Tx frame sync length set to one-bit-long-frame (TCR[TFSL] = 1)
• Rx frame sync length set to one-bit-long-frame (RCR[RFSL] = 1)
• Tx shifting w.r.t. bit 0 of TXSR (TCR[TXBIT0] = 1)
• Rx shifting w.r.t. bit 0 of RXSR (RCR[RXBIT0] = 1)
Set the TCCR[WL, DC] bits to configure the data transmission.
The word length is variable in I
2
S slave mode and the RCCR[WL] bits determine the
number of bits that contain valid data. The actual word length is determined by the
external codec. The external I
2
S master sends a frame sync according to the I
2
S protocol
(early, word wide, and active low). The I
2
S internally operates so each frame sync
transition is the start of a new frame (the RCCR[WL] bits determine the number of bits to
be transmitted/received). After one data word has been transferred, the I
2
S waits for the
next frame sync transition to start operation in the next time slot. Transmit and receive
mask bits should not be used in I
2
S slave mode.
Functional description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1504 Freescale Semiconductor, Inc.