Information

In the next example, the oversampling clock (network clock) clock is 11.2896 MHz. A
16-bit word network mode with TCCR[DC] = 1, TCCR[PM] = 3, TCCR[PSR] = 0,
TCCR[DIV2] = 0, a bit clock rate of 1.4112 MHz is generated. Since the 16-bit word rate
is equal to two, the sampling rate (or frame sync rate) would be 1.4112/(2×16) = 44.1
kHz.
The following table shows examples of programming the TCCR[PSR] and TCCR[PM]
bits to generate various bit clock (STCK) frequencies.
Table 47-51. I
2
S bit clock and frame rate as a function of PSR, PM, and
DIV2
Bits/
word
Words/
frame
MCLK/network clock
freq (MHz)
TCCR Bit clock
(kHz)
STCK
Frame
rate
(kHz)
DIV2 PSR PM WL DC
16 1 12.288 0 0 47 7 0 128 8
16 2 12.288 0 0 23 7 1 256 8
16 4 12.288 0 0 11 7 3 512 8
16 1 12.288 0 0 31 7 0 192 12
16 2 12.288 0 0 15 7 1 384 12
16 4 12.288 0 0 7 7 3 768 12
16 1 12.288 0 0 23 7 0 256 16
16 2 12.288 0 0 11 7 1 512 16
16 4 12.288 0 0 5 7 3 1024 16
16 1 12.288 0 0 15 7 0 384 24
16 2 12.288 0 0 7 7 1 768 24
16 4 12.288 0 0 3 7 3 1536 24
16 1 12.288 0 0 11 7 0 512 32
16 2 12.288 0 0 5 7 1 1024 32
16 4 12.288 0 0 2 7 3 2048 32
16 1 12.288 0 0 15 7 0 768 48
16 2 12.288 0 0 3 7 1 1536 48
16 4 12.288 0 0 1 7 3 3072 48
16 1 11.2896 0 0 31 7 0 176.4 11.025
16 2 11.2896 0 0 15 7 1 352.8 11.025
16 4 11.2896 0 0 7 7 3 705.6 11.025
16 1 11.2896 0 0 15 7 0 352.8 22.05
16 2 11.2896 0 0 7 7 1 705.6 22.05
16 4 11.2896 0 0 3 7 3 1411.2 22.05
Table continues on the next page...
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1511