Information

Table 47-53. Data alignment (continued)
24-bit lsb aligned 23:0
24-bit msb aligned 23:0
In addition, if lsb alignment is selected, the receive data can be zero-extended or sign-
extended.
• In zero-extension, all bits above the most significant bit are 0s. This format is useful
when data is stored in a pure integer format.
• In sign-extension, all bits above the most significant bit are equal to the most
significant bit. This format is useful when data is stored in a fixed-point integer
format (which implies fractional values).
The RCR[RXEXT] bit controls receive data extension. Transmit data used with lsb
alignment has no concept of sign/zero-extension. Unused bits above the most significant
bit are simply ignored.
When configured in I
2
S or AC97 mode, the I
2
S forces the selection of lsb alignment.
However, RXEXT chooses zero-extension and sign-extension.
47.4.4 Receive interrupt enable bit description
If the receive FIFO is not enabled and the IER[RIE] and CR[RE] bits are set:
• an interrupt occurs when the corresponding I
2
S receive data ready (ISR[RDR0/1]) bit
is set
• one value can be read from the RX register (one each in two-channel mode)
If the receive FIFO is enabled and the IER[RIE] and CR[RE] bits are set:
• an interrupt occurs when either of the I
2
S receive FIFO full (ISR[RFF0/1) bits is set
• a maximum of 15 values are available to be read (15 values per channel in two-
channel mode)
If the IER[RIE] bit is cleared, these interrupts are disabled. However, the RFF0/1 and
RDR0/1 bits indicate the receive data register full condition. Reading the RX registers
clears the ISR[RDR] bits, thus clearing the pending interrupt. Two receive data interrupts
(two per channel in two-channel mode) are available: receive data with exception status
and receive data without exception. The following table shows the conditions under
which these interrupts are generated.
Functional description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1514 Freescale Semiconductor, Inc.