Information

The following figure is illustrates a transmission case where:
• TCR[TXDIR] and TCR[TFDIR] are set
• CR[TFRCLKDIS] is set a few frames after clearing CR[TE]
• ISR[TRFC] is set at the frame boundary after CR[TE] is cleared. Once software
services this interrupt and later sets CR[TFRCLKDIS] bit, the ISR[TRFC] bit is set
again at next frame boundary.
CLK
FS
Tx Data
CR[TE]
CR[TFCLDIS]
ISR[TFRC]
w1c
Figure 47-60. CR[TFRCLKDIS] assertion in subsequent frame after disabling CR[TE]
47.4.7 Reset
The I
2
S is affected by the following types of reset:
• Power-on reset—This reset clears the CR[I2SEN] bit, which disables the I
2
S. All
other status and control bits in the I
2
S are affected as described in Memory map/
register definition.
• I
2
S reset—The I
2
S reset is generated when the CR[I2SEN] bit is cleared. The I
2
S
status bits are reset to the same state produced by the power-on reset. The I
2
S control
bits, including those in CR register, are unaffected. The I
2
S reset is useful for
selective reset of the I
2
S, without changing the present I
2
S control bits and without
affecting other peripherals.
47.5 Initialization/application information
The correct sequence to initialize the I
2
S is as follows:
1. Issue a power-on or I
2
S reset (CR[I2SEN] = 0).
Chapter 47 Integrated interchip sound (I2S)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1517