Information

48.1.3.1 Detailed signal description
Table 48-2. GPIO interface-detailed signal descriptions
Signal I/O Description
PORTA[31:0]
PORTB[31:0]
PORTC[31:0]
PORTD[31:0]
PORTE[31:0]
I/O General purpose input/output.
State meaning Asserted - pin is logic one.
Negated - pin is logic zero.
Timing Assertion - when output,
occurs on rising edge of the
system clock. For input, may
occur at any time and input
may be asserted
asynchronously to the system
clock.
Negation - when output,
occurs on rising edge of the
system clock. For input, may
occur at any time and input
may be asserted
asynchronously to the system
clock.
48.2 Memory map and register definition
Any read or write access to the GPIO memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states, except
error accesses which complete with one wait state.
GPIO memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400F_F000 Port Data Output Register (GPIOA_PDOR) 32 R/W 0000_0000h
48.2.1/
1526
400F_F004 Port Set Output Register (GPIOA_PSOR) 32
W
(always
reads
zero)
0000_0000h
48.2.2/
1526
400F_F008 Port Clear Output Register (GPIOA_PCOR) 32
W
(always
reads
zero)
0000_0000h
48.2.3/
1527
400F_F00C Port Toggle Output Register (GPIOA_PTOR) 32
W
(always
0000_0000h
48.2.4/
1527
Table continues on the next page...
Chapter 48 General purpose input/output (GPIO)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1523