Information

Section Number Title Page
Chapter 20
Direct memory access multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................401
20.1.1 Overview......................................................................................................................................................401
20.1.2 Features........................................................................................................................................................402
20.1.3 Modes of operation......................................................................................................................................402
20.2 External signal description............................................................................................................................................403
20.3 Memory map/register definition...................................................................................................................................403
20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................404
20.4 Functional description...................................................................................................................................................405
20.4.1 DMA channels with periodic triggering capability......................................................................................405
20.4.2 DMA channels with no triggering capability...............................................................................................408
20.4.3 "Always enabled" DMA sources.................................................................................................................408
20.5 Initialization/application information...........................................................................................................................409
20.5.1 Reset.............................................................................................................................................................409
20.5.2 Enabling and configuring sources................................................................................................................409
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................413
21.1.1 Block diagram..............................................................................................................................................413
21.1.2 Block parts...................................................................................................................................................414
21.1.3 Features........................................................................................................................................................416
21.2 Modes of operation.......................................................................................................................................................417
21.3 Memory map/register definition...................................................................................................................................417
21.3.1 Control Register (DMA_CR).......................................................................................................................432
21.3.2 Error Status Register (DMA_ES)................................................................................................................434
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................436
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................438
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................440
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
16 Freescale Semiconductor, Inc.