Information

4.6 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select
processor-local modules. These resources are only accessible from the core; other system
masters do not have access to them.
Table 4-4. PPB memory map
System 32-bit Address Range Resource
0xE000_0000–0xE000_0FFF Instrumentation Trace Macrocell (ITM)
0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT)
0xE000_2000–0xE000_2FFF Flash Patch and Breakpoint (FPB)
0xE000_3000–0xE000_DFFF Reserved
0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC)
0xE000_F000–0xE003_FFFF Reserved
0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU)
0xE004_1000–0xE004_1FFF Embedded Trace Macrocell (ETM)
0xE004_2000–0xE004_2FFF Embedded Trace Buffer (ETB)
0xE004_3000–0xE004_3FFF Embedded Trace Funnel
0xE004_4000–0xE007_FFFF Reserved
0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM)(including ETB Almost Full)
0xE008_1000–0xE008_1FFF Reserved
0xE008_2000–0xE00F_EFFF Reserved
0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components
Private Peripheral Bus (PPB) memory map
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
162 Freescale Semiconductor, Inc.