Information

Table 5-1. Clock Summary (continued)
Clock name Run mode
clock frequency
VLPR mode
clock frequency
Clock source Clock is disabled
when…
FlexBus clock
(FB_CLK)
Up to 50 MHz Up to 2 MHz MCGOUTCLK clock
divider
In all stop modes or
FlexBus disabled
Flash clock Up to 25 MHz Up to 1 MHz MCGOUTCLK clock
divider
In all stop modes
Internal reference
(MCGIRCLK)
30-40 kHz or 2 MHz 2 MHz only MCG MCG_C1[IRCLKEN]
cleared,
Stop mode and
MCG_C1[IREFSTEN]
cleared, or
VLPS/LLS/VLLS mode
External reference
(OSCERCLK)
Up to 50 MHz
(bypass),
30-40 kHz, or
4-32 MHz (crystal)
Up to 4 MHz (bypass),
30-40 kHz (low-range
crystal) or
Up to 4 MHz (high-
range crystal)
System OSC System OSC's
OSC_CR[ERCLKEN]
cleared, or
Stop mode and
OSC_CR[EREFSTEN]
cleared
External reference
32kHz
(ERCLK32K)
30-40 kHz 30-40 kHz System OSC or RTC
OSC depending on
SIM_SOPT1[OSC32K
SEL]
System OSC's
OSC_CR[ERCLKEN]
cleared or
RTC's RTC_CR[OSCE]
cleared
RTC_CLKOUT 1 Hz 1 Hz RTC clock Clock is disabled in
LLS and VLLSx modes
LPO 1 kHz 1 kHz PMC Available in all power
modes
I2S master clock Up to 50 MHz N/A System clock,
MCGPLLCLK, or
MCGFLLCLK with
fractional clock divider,
OSCERCLK, or
I2S_CLKIN
I
2
S is disabled
SDHC clock Up to 50 MHz N/A System clock,
MCGPLLCLK/
MCGFLLCLK, or
OSCERCLK
SDHC is disabled
TRACE clock Up to 100 MHz Up to 2 MHz System clock or
MCGOUTCLK
Trace is disabled
Clock definitions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
166 Freescale Semiconductor, Inc.