Information

5.5 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. Each
divider is programmable from a divide-by-1 through divide-by-16 setting. The following
requirements must be met when configuring the clocks for this device:
1. The core and system clock frequencies must be 100 MHz or slower.
2. The bus clock frequency must be programmed to 50 MHz or less and an integer
divide of the core clock.
3. The flash clock frequency must be programmed to 25 MHz or less and an integer
divide of the bus clock.
4. The FlexBus clock frequency must be programmed to be less than or equal to the bus
clock frequency.
The following are a few of the more common clock configurations for this device:
Option 1:
Clock Frequency
Core clock 50 MHz
System clock 50 MHz
Bus clock 50 MHz
FlexBus clock 50 MHz
Flash clock 25 MHz
Option 2:
Clock Frequency
Core clock 100 MHz
System clock 100 MHz
Bus clock 50 MHz
FlexBus clock 25 MHz
Flash clock 25 MHz
Option 3:
Clock Frequency
Core clock 96 MHz
System clock 96 MHz
Bus clock 48 MHz
FlexBus clock 48 MHz
Flash clock 24 MHz
Chapter 5 Clock Distribution
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 167